Pfthb

Referring to my previous post:
Error (10482): VHDL error: object "select_vector" is used but not declared

I converted my code from VHDL to verilog, but I'm getting this error now:

(Error (10734): Verilog HDL error at SWSelector.v(13): selector is not
a constant),

Any suggestions how do I deal with it? There are 8 possibilities for selector switch which are coming from a decoder. So whenever the value of selector matches 3'b000, I want rq to be assigned to requests. Here is my code:

module SWSelector(
input [7:0] rq,
input [2:0] selector,
output [7:0] request
);
localparam NUM=3'b000;
generate
genvar i;
for(i=0;i<7;i=i+1)
 begin: label
 if(selector == NUM)
 begin
 assign request[i] = rq[i];
 end 
 else 
 begin
 assign request[i]=0;
 end
 end
endgenerate
endmodule

Since your if-statement is in a generate, you're asking the tool to pre-evaluate what selector is set to in order to figure out selecter == NUM evaluates to, but your tool doesn't know because it's a signal, not a parameter.

You want to use the generate to create an always block that you can check the value of selector in, like so:

module SWSelector(
 input [7:0] rq,
 input [2:0] selector,
 output reg [7:0] request
);
 localparam NUM=3'b000;
 generate
 genvar i;
 for(i=0;i<7;i=i+1)
 begin: label
 always @* begin
 if(selector == NUM)
 request[i] = rq[i];
 else
 request[i]=0;
 end
 end
 endgenerate
endmodule

Or, as toolic said, you can use a ternary and an assign.

Edit:

Without generate:

module SWSelector(
 input [7:0] rq,
 input [2:0] selector,
 output reg [7:0] request
);
 localparam NUM=3'b000;

 integer i;
 always @* begin
 for(i=0;i<7;i=i+1) 
 if(selector == NUM)
 request[i] = rq[i];
 else
 request[i]=0;
 end
endmodule