Samsung DDR4: How read/write on mode register?
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I have a Samsun DRAM with a K4A8G085WB-BCTD DDR4.
The device operation specification (here) says you can work with mode register through the MRS instruction [section 1.4].
I'd like to know if TRR (target row refresh) [section 2.34] is enabled or not. It says I can read the MR4 register discovering if it is active or I can write into it to activate it. However, How can I write/read the mode register practically? What kind of register is MR4?
c hardware ram cpu-registers hardware-programming
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I have a Samsun DRAM with a K4A8G085WB-BCTD DDR4.
The device operation specification (here) says you can work with mode register through the MRS instruction [section 1.4].
I'd like to know if TRR (target row refresh) [section 2.34] is enabled or not. It says I can read the MR4 register discovering if it is active or I can write into it to activate it. However, How can I write/read the mode register practically? What kind of register is MR4?
c hardware ram cpu-registers hardware-programming
add a comment |
I have a Samsun DRAM with a K4A8G085WB-BCTD DDR4.
The device operation specification (here) says you can work with mode register through the MRS instruction [section 1.4].
I'd like to know if TRR (target row refresh) [section 2.34] is enabled or not. It says I can read the MR4 register discovering if it is active or I can write into it to activate it. However, How can I write/read the mode register practically? What kind of register is MR4?
c hardware ram cpu-registers hardware-programming
I have a Samsun DRAM with a K4A8G085WB-BCTD DDR4.
The device operation specification (here) says you can work with mode register through the MRS instruction [section 1.4].
I'd like to know if TRR (target row refresh) [section 2.34] is enabled or not. It says I can read the MR4 register discovering if it is active or I can write into it to activate it. However, How can I write/read the mode register practically? What kind of register is MR4?
c hardware ram cpu-registers hardware-programming
c hardware ram cpu-registers hardware-programming
asked Nov 15 '18 at 17:18
Emanuele VannacciEmanuele Vannacci
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As far as I can tell, this is not a command that would be issued from software on the host cpu to the DRAM module, but either by the DDR controller on the motherboard (or integrated with the cpu) to the DRAM module, or by a controller chip on the module to the individual DDR chips. There might be some way to get Intel's controller to pass commands through, but it's more likely that there's some Intel model-specific register (documented or undocumented, possibly exposed only through BIOS/firmware) to control the feature at a higher level.
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1 Answer
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1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
As far as I can tell, this is not a command that would be issued from software on the host cpu to the DRAM module, but either by the DDR controller on the motherboard (or integrated with the cpu) to the DRAM module, or by a controller chip on the module to the individual DDR chips. There might be some way to get Intel's controller to pass commands through, but it's more likely that there's some Intel model-specific register (documented or undocumented, possibly exposed only through BIOS/firmware) to control the feature at a higher level.
add a comment |
As far as I can tell, this is not a command that would be issued from software on the host cpu to the DRAM module, but either by the DDR controller on the motherboard (or integrated with the cpu) to the DRAM module, or by a controller chip on the module to the individual DDR chips. There might be some way to get Intel's controller to pass commands through, but it's more likely that there's some Intel model-specific register (documented or undocumented, possibly exposed only through BIOS/firmware) to control the feature at a higher level.
add a comment |
As far as I can tell, this is not a command that would be issued from software on the host cpu to the DRAM module, but either by the DDR controller on the motherboard (or integrated with the cpu) to the DRAM module, or by a controller chip on the module to the individual DDR chips. There might be some way to get Intel's controller to pass commands through, but it's more likely that there's some Intel model-specific register (documented or undocumented, possibly exposed only through BIOS/firmware) to control the feature at a higher level.
As far as I can tell, this is not a command that would be issued from software on the host cpu to the DRAM module, but either by the DDR controller on the motherboard (or integrated with the cpu) to the DRAM module, or by a controller chip on the module to the individual DDR chips. There might be some way to get Intel's controller to pass commands through, but it's more likely that there's some Intel model-specific register (documented or undocumented, possibly exposed only through BIOS/firmware) to control the feature at a higher level.
answered Nov 15 '18 at 17:56
R..R..
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