How to set inputs in vhdl (ISE Design Suite) without a testbench?
-2
I want to quickly test something without having to go through the long process of creating a testbench. Is there any way in which I can just simply change the input of A from "UUUU" to "0111", for example?
vhdl
asked Nov 13 '18 at 12:52
Jaime FernándezJaime Fernández
423
add a comment |
-2
I want to quickly test something without having to go through the long process of creating a testbench. Is there any way in which I can just simply change the input of A from "UUUU" to "0111", for example?
vhdl
asked Nov 13 '18 at 12:52
Jaime FernándezJaime Fernández
423
Before you keep downvoting me, yes I have searched for answers before posting and there simply aren't. I will be evaluated and I won't have time to create a testbench during the exam, and I'm sure there must be an easy way to do this but I can't figure it out
– Jaime Fernández
Nov 13 '18 at 13:48
There will be something proprietary that your simulator will do, but I very much doubt it would be quicker than dong a very simple testbench - literally five minutes work, frankly.
– Matthew Taylor
Nov 13 '18 at 14:03
1
Time taken to type in and run this testbench from scratch - 3:30 - including wasting 45s debugging some issue with EDA Playground (It seemed to think it was simulating SystemVerilog for some reason).
– Matthew Taylor
Nov 13 '18 at 14:09
1
And it gets faster after three, four test benches as I tend to copy-paste standard sections like generating clock(s) and reset.
– Oldfart
Nov 13 '18 at 14:44
1
Right-click on the signal in waveform window and you'll find aForce constantoption. It is easy to do this for one or two signals. As the design grows, it gets more and more time-consuming and difficult. Writing a testbench is the right way. It is beneficial as pointed out by earlier comments. Moreover, with ISE, you can also generate a template testbench specifically for the entity/component you want to test. Tool will generate a nice template. You only have to add stimuli and correct your clock and reset port-names. It doesn't get easier than that.!
– Vinay Madapura
Nov 14 '18 at 9:17
add a comment |
-2
-2
-2
I want to quickly test something without having to go through the long process of creating a testbench. Is there any way in which I can just simply change the input of A from "UUUU" to "0111", for example?
vhdl
asked Nov 13 '18 at 12:52
Jaime FernándezJaime Fernández
423
I want to quickly test something without having to go through the long process of creating a testbench. Is there any way in which I can just simply change the input of A from "UUUU" to "0111", for example?
vhdl
vhdl
asked Nov 13 '18 at 12:52
Jaime FernándezJaime Fernández
423
asked Nov 13 '18 at 12:52
Jaime FernándezJaime Fernández
423
asked Nov 13 '18 at 12:52
Jaime FernándezJaime Fernández
423
asked Nov 13 '18 at 12:52
Jaime FernándezJaime Fernández
423
asked Nov 13 '18 at 12:52
Jaime FernándezJaime Fernández
423
423
Before you keep downvoting me, yes I have searched for answers before posting and there simply aren't. I will be evaluated and I won't have time to create a testbench during the exam, and I'm sure there must be an easy way to do this but I can't figure it out
– Jaime Fernández
Nov 13 '18 at 13:48
There will be something proprietary that your simulator will do, but I very much doubt it would be quicker than dong a very simple testbench - literally five minutes work, frankly.
– Matthew Taylor
Nov 13 '18 at 14:03
1
Time taken to type in and run this testbench from scratch - 3:30 - including wasting 45s debugging some issue with EDA Playground (It seemed to think it was simulating SystemVerilog for some reason).
– Matthew Taylor
Nov 13 '18 at 14:09
1
And it gets faster after three, four test benches as I tend to copy-paste standard sections like generating clock(s) and reset.
– Oldfart
Nov 13 '18 at 14:44
1
Right-click on the signal in waveform window and you'll find aForce constantoption. It is easy to do this for one or two signals. As the design grows, it gets more and more time-consuming and difficult. Writing a testbench is the right way. It is beneficial as pointed out by earlier comments. Moreover, with ISE, you can also generate a template testbench specifically for the entity/component you want to test. Tool will generate a nice template. You only have to add stimuli and correct your clock and reset port-names. It doesn't get easier than that.!
– Vinay Madapura
Nov 14 '18 at 9:17
add a comment |
Before you keep downvoting me, yes I have searched for answers before posting and there simply aren't. I will be evaluated and I won't have time to create a testbench during the exam, and I'm sure there must be an easy way to do this but I can't figure it out
– Jaime Fernández
Nov 13 '18 at 13:48
There will be something proprietary that your simulator will do, but I very much doubt it would be quicker than dong a very simple testbench - literally five minutes work, frankly.
– Matthew Taylor
Nov 13 '18 at 14:03
1
Time taken to type in and run this testbench from scratch - 3:30 - including wasting 45s debugging some issue with EDA Playground (It seemed to think it was simulating SystemVerilog for some reason).
– Matthew Taylor
Nov 13 '18 at 14:09
1
And it gets faster after three, four test benches as I tend to copy-paste standard sections like generating clock(s) and reset.
– Oldfart
Nov 13 '18 at 14:44
1
Right-click on the signal in waveform window and you'll find aForce constantoption. It is easy to do this for one or two signals. As the design grows, it gets more and more time-consuming and difficult. Writing a testbench is the right way. It is beneficial as pointed out by earlier comments. Moreover, with ISE, you can also generate a template testbench specifically for the entity/component you want to test. Tool will generate a nice template. You only have to add stimuli and correct your clock and reset port-names. It doesn't get easier than that.!
– Vinay Madapura
Nov 14 '18 at 9:17
Before you keep downvoting me, yes I have searched for answers before posting and there simply aren't. I will be evaluated and I won't have time to create a testbench during the exam, and I'm sure there must be an easy way to do this but I can't figure it out
– Jaime Fernández
Nov 13 '18 at 13:48
Before you keep downvoting me, yes I have searched for answers before posting and there simply aren't. I will be evaluated and I won't have time to create a testbench during the exam, and I'm sure there must be an easy way to do this but I can't figure it out
– Jaime Fernández
Nov 13 '18 at 13:48
There will be something proprietary that your simulator will do, but I very much doubt it would be quicker than dong a very simple testbench - literally five minutes work, frankly.
– Matthew Taylor
Nov 13 '18 at 14:03
There will be something proprietary that your simulator will do, but I very much doubt it would be quicker than dong a very simple testbench - literally five minutes work, frankly.
– Matthew Taylor
Nov 13 '18 at 14:03
1
1
Time taken to type in and run this testbench from scratch - 3:30 - including wasting 45s debugging some issue with EDA Playground (It seemed to think it was simulating SystemVerilog for some reason).
– Matthew Taylor
Nov 13 '18 at 14:09
Time taken to type in and run this testbench from scratch - 3:30 - including wasting 45s debugging some issue with EDA Playground (It seemed to think it was simulating SystemVerilog for some reason).
– Matthew Taylor
Nov 13 '18 at 14:09
1
1
And it gets faster after three, four test benches as I tend to copy-paste standard sections like generating clock(s) and reset.
– Oldfart
Nov 13 '18 at 14:44
And it gets faster after three, four test benches as I tend to copy-paste standard sections like generating clock(s) and reset.
– Oldfart
Nov 13 '18 at 14:44
1
1
Right-click on the signal in waveform window and you'll find a
Force constant option. It is easy to do this for one or two signals. As the design grows, it gets more and more time-consuming and difficult. Writing a testbench is the right way. It is beneficial as pointed out by earlier comments. Moreover, with ISE, you can also generate a template testbench specifically for the entity/component you want to test. Tool will generate a nice template. You only have to add stimuli and correct your clock and reset port-names. It doesn't get easier than that.!– Vinay Madapura
Nov 14 '18 at 9:17
Right-click on the signal in waveform window and you'll find a
Force constant option. It is easy to do this for one or two signals. As the design grows, it gets more and more time-consuming and difficult. Writing a testbench is the right way. It is beneficial as pointed out by earlier comments. Moreover, with ISE, you can also generate a template testbench specifically for the entity/component you want to test. Tool will generate a nice template. You only have to add stimuli and correct your clock and reset port-names. It doesn't get easier than that.!– Vinay Madapura
Nov 14 '18 at 9:17
add a comment |
1 Answer
1
active
oldest
votes
0
Add default port values like in
entity foo is
port (
bar1 : in std_logic := '0';
bar2 : out std_logic := '0'
);
end entity foo;
Else forcing the value in the simulator works fine, as commented
answered Nov 16 '18 at 0:08
B. GoB. Go
14017
add a comment |
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1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
0
Add default port values like in
entity foo is
port (
bar1 : in std_logic := '0';
bar2 : out std_logic := '0'
);
end entity foo;
Else forcing the value in the simulator works fine, as commented
answered Nov 16 '18 at 0:08
B. GoB. Go
14017
add a comment |
0
Add default port values like in
entity foo is
port (
bar1 : in std_logic := '0';
bar2 : out std_logic := '0'
);
end entity foo;
Else forcing the value in the simulator works fine, as commented
answered Nov 16 '18 at 0:08
B. GoB. Go
14017
add a comment |
0
0
0
Add default port values like in
entity foo is
port (
bar1 : in std_logic := '0';
bar2 : out std_logic := '0'
);
end entity foo;
Else forcing the value in the simulator works fine, as commented
answered Nov 16 '18 at 0:08
B. GoB. Go
14017
Add default port values like in
entity foo is
port (
bar1 : in std_logic := '0';
bar2 : out std_logic := '0'
);
end entity foo;
Else forcing the value in the simulator works fine, as commented
answered Nov 16 '18 at 0:08
B. GoB. Go
14017
answered Nov 16 '18 at 0:08
B. GoB. Go
14017
answered Nov 16 '18 at 0:08
B. GoB. Go
14017
answered Nov 16 '18 at 0:08
B. GoB. Go
14017
14017
add a comment |
add a comment |
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Before you keep downvoting me, yes I have searched for answers before posting and there simply aren't. I will be evaluated and I won't have time to create a testbench during the exam, and I'm sure there must be an easy way to do this but I can't figure it out
– Jaime Fernández
Nov 13 '18 at 13:48
There will be something proprietary that your simulator will do, but I very much doubt it would be quicker than dong a very simple testbench - literally five minutes work, frankly.
– Matthew Taylor
Nov 13 '18 at 14:03
1
Time taken to type in and run this testbench from scratch - 3:30 - including wasting 45s debugging some issue with EDA Playground (It seemed to think it was simulating SystemVerilog for some reason).
– Matthew Taylor
Nov 13 '18 at 14:09
1
And it gets faster after three, four test benches as I tend to copy-paste standard sections like generating clock(s) and reset.
– Oldfart
Nov 13 '18 at 14:44
1
Right-click on the signal in waveform window and you'll find a
Force constantoption. It is easy to do this for one or two signals. As the design grows, it gets more and more time-consuming and difficult. Writing a testbench is the right way. It is beneficial as pointed out by earlier comments. Moreover, with ISE, you can also generate a template testbench specifically for the entity/component you want to test. Tool will generate a nice template. You only have to add stimuli and correct your clock and reset port-names. It doesn't get easier than that.!– Vinay Madapura
Nov 14 '18 at 9:17