Why the RISC instruction sets usually do not contain register to register copy instruction?
2
I had this question on my exam and i am confused because as far as i know that
move $t0, $a0 # COPY $A0 TO $T0
in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something?
assembly cpu-architecture instruction-set risc
edited Nov 13 '18 at 17:32
Peter Cordes
127k18190326
asked Nov 13 '18 at 17:14
roffensiveroffensive
15810
add a comment |
2
I had this question on my exam and i am confused because as far as i know that
move $t0, $a0 # COPY $A0 TO $T0
in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something?
assembly cpu-architecture instruction-set risc
edited Nov 13 '18 at 17:32
Peter Cordes
127k18190326
asked Nov 13 '18 at 17:14
roffensiveroffensive
15810
If they have zero register like MIPS (and most RISC-like do), thenadd/orare "obvious" substitutions. Without zero register it would made me scratch my head for some time.
– Ped7g
Nov 13 '18 at 18:51
1
Also it's maybe not obvious why, if you missed that part about how machine code is encoded. On RISC machines usually every instruction has size of exactly one machine "word" (32 bits quite often). So the fewer instructions you need to encode, the more bits are left for registers specification and/or immediate values. Notice that 32 bit instruction can't contain both instruction opcode and 32 bit immediate, so that's why loading full 32b constant on 32b RISC CPU into register usually takes either 2-3 normal instruction, or the constant is fetched from memory. Nomove= more bits for others.
– Ped7g
Nov 14 '18 at 0:16
add a comment |
2
2
2
I had this question on my exam and i am confused because as far as i know that
move $t0, $a0 # COPY $A0 TO $T0
in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something?
assembly cpu-architecture instruction-set risc
edited Nov 13 '18 at 17:32
Peter Cordes
127k18190326
asked Nov 13 '18 at 17:14
roffensiveroffensive
15810
I had this question on my exam and i am confused because as far as i know that
move $t0, $a0 # COPY $A0 TO $T0
in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something?
assembly cpu-architecture instruction-set risc
assembly cpu-architecture instruction-set risc
edited Nov 13 '18 at 17:32
Peter Cordes
127k18190326
asked Nov 13 '18 at 17:14
roffensiveroffensive
15810
edited Nov 13 '18 at 17:32
Peter Cordes
127k18190326
asked Nov 13 '18 at 17:14
roffensiveroffensive
15810
edited Nov 13 '18 at 17:32
Peter Cordes
127k18190326
edited Nov 13 '18 at 17:32
Peter Cordes
127k18190326
edited Nov 13 '18 at 17:32
Peter Cordes
127k18190326
127k18190326
asked Nov 13 '18 at 17:14
roffensiveroffensive
15810
asked Nov 13 '18 at 17:14
roffensiveroffensive
15810
asked Nov 13 '18 at 17:14
roffensiveroffensive
15810
15810
If they have zero register like MIPS (and most RISC-like do), thenadd/orare "obvious" substitutions. Without zero register it would made me scratch my head for some time.
– Ped7g
Nov 13 '18 at 18:51
1
Also it's maybe not obvious why, if you missed that part about how machine code is encoded. On RISC machines usually every instruction has size of exactly one machine "word" (32 bits quite often). So the fewer instructions you need to encode, the more bits are left for registers specification and/or immediate values. Notice that 32 bit instruction can't contain both instruction opcode and 32 bit immediate, so that's why loading full 32b constant on 32b RISC CPU into register usually takes either 2-3 normal instruction, or the constant is fetched from memory. Nomove= more bits for others.
– Ped7g
Nov 14 '18 at 0:16
add a comment |
If they have zero register like MIPS (and most RISC-like do), thenadd/orare "obvious" substitutions. Without zero register it would made me scratch my head for some time.
– Ped7g
Nov 13 '18 at 18:51
1
Also it's maybe not obvious why, if you missed that part about how machine code is encoded. On RISC machines usually every instruction has size of exactly one machine "word" (32 bits quite often). So the fewer instructions you need to encode, the more bits are left for registers specification and/or immediate values. Notice that 32 bit instruction can't contain both instruction opcode and 32 bit immediate, so that's why loading full 32b constant on 32b RISC CPU into register usually takes either 2-3 normal instruction, or the constant is fetched from memory. Nomove= more bits for others.
– Ped7g
Nov 14 '18 at 0:16
If they have zero register like MIPS (and most RISC-like do), then
add/or are "obvious" substitutions. Without zero register it would made me scratch my head for some time.– Ped7g
Nov 13 '18 at 18:51
If they have zero register like MIPS (and most RISC-like do), then
add/or are "obvious" substitutions. Without zero register it would made me scratch my head for some time.– Ped7g
Nov 13 '18 at 18:51
1
1
Also it's maybe not obvious why, if you missed that part about how machine code is encoded. On RISC machines usually every instruction has size of exactly one machine "word" (32 bits quite often). So the fewer instructions you need to encode, the more bits are left for registers specification and/or immediate values. Notice that 32 bit instruction can't contain both instruction opcode and 32 bit immediate, so that's why loading full 32b constant on 32b RISC CPU into register usually takes either 2-3 normal instruction, or the constant is fetched from memory. No
move = more bits for others.– Ped7g
Nov 14 '18 at 0:16
Also it's maybe not obvious why, if you missed that part about how machine code is encoded. On RISC machines usually every instruction has size of exactly one machine "word" (32 bits quite often). So the fewer instructions you need to encode, the more bits are left for registers specification and/or immediate values. Notice that 32 bit instruction can't contain both instruction opcode and 32 bit immediate, so that's why loading full 32b constant on 32b RISC CPU into register usually takes either 2-3 normal instruction, or the constant is fetched from memory. No
move = more bits for others.– Ped7g
Nov 14 '18 at 0:16
add a comment |
1 Answer
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4
Move is a pseudoinstruction, and when assembled will really be a different instruction.
For instance
move $t0, $zero gets implemented as addu $t0, $zero, $zero
answered Nov 13 '18 at 17:25
lostbardlostbard
3,1231412
Ok, and do u know the answer for the initial question?
– roffensive
Nov 13 '18 at 17:29
2
that is the answer - there is no move - it is really add
– lostbard
Nov 13 '18 at 17:29
add a comment |
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1 Answer
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1 Answer
1
active
oldest
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active
oldest
votes
active
oldest
votes
4
Move is a pseudoinstruction, and when assembled will really be a different instruction.
For instance
move $t0, $zero gets implemented as addu $t0, $zero, $zero
answered Nov 13 '18 at 17:25
lostbardlostbard
3,1231412
Ok, and do u know the answer for the initial question?
– roffensive
Nov 13 '18 at 17:29
2
that is the answer - there is no move - it is really add
– lostbard
Nov 13 '18 at 17:29
add a comment |
4
Move is a pseudoinstruction, and when assembled will really be a different instruction.
For instance
move $t0, $zero gets implemented as addu $t0, $zero, $zero
answered Nov 13 '18 at 17:25
lostbardlostbard
3,1231412
Ok, and do u know the answer for the initial question?
– roffensive
Nov 13 '18 at 17:29
2
that is the answer - there is no move - it is really add
– lostbard
Nov 13 '18 at 17:29
add a comment |
4
4
4
Move is a pseudoinstruction, and when assembled will really be a different instruction.
For instance
move $t0, $zero gets implemented as addu $t0, $zero, $zero
answered Nov 13 '18 at 17:25
lostbardlostbard
3,1231412
Move is a pseudoinstruction, and when assembled will really be a different instruction.
For instance
move $t0, $zero gets implemented as addu $t0, $zero, $zero
answered Nov 13 '18 at 17:25
lostbardlostbard
3,1231412
answered Nov 13 '18 at 17:25
lostbardlostbard
3,1231412
answered Nov 13 '18 at 17:25
lostbardlostbard
3,1231412
answered Nov 13 '18 at 17:25
lostbardlostbard
3,1231412
3,1231412
Ok, and do u know the answer for the initial question?
– roffensive
Nov 13 '18 at 17:29
2
that is the answer - there is no move - it is really add
– lostbard
Nov 13 '18 at 17:29
add a comment |
Ok, and do u know the answer for the initial question?
– roffensive
Nov 13 '18 at 17:29
2
that is the answer - there is no move - it is really add
– lostbard
Nov 13 '18 at 17:29
Ok, and do u know the answer for the initial question?
– roffensive
Nov 13 '18 at 17:29
Ok, and do u know the answer for the initial question?
– roffensive
Nov 13 '18 at 17:29
2
2
that is the answer - there is no move - it is really add
– lostbard
Nov 13 '18 at 17:29
that is the answer - there is no move - it is really add
– lostbard
Nov 13 '18 at 17:29
add a comment |
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If they have zero register like MIPS (and most RISC-like do), then
add/orare "obvious" substitutions. Without zero register it would made me scratch my head for some time.– Ped7g
Nov 13 '18 at 18:51
1
Also it's maybe not obvious why, if you missed that part about how machine code is encoded. On RISC machines usually every instruction has size of exactly one machine "word" (32 bits quite often). So the fewer instructions you need to encode, the more bits are left for registers specification and/or immediate values. Notice that 32 bit instruction can't contain both instruction opcode and 32 bit immediate, so that's why loading full 32b constant on 32b RISC CPU into register usually takes either 2-3 normal instruction, or the constant is fetched from memory. No
move= more bits for others.– Ped7g
Nov 14 '18 at 0:16